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SC Conference - Activity Details
A Multi-level Parallel Simulation Approach to Electron Transport in Nano-scale Transistors
Authors:
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Mathieu Luisier
(Purdue University)
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Gerhard Klimeck
(Purdue University)
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Papers Session
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Large-Scale Applications
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Tuesday, 01:30PM - 02:00PM
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Room Ballroom E
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Abstract:
Physics-based simulation of electron transport in nanoelectronic
devices requires the solution of thousands of highly complex equations
to obtain the output characteristics of one single input voltage. The
only way to obtain a complete set of bias points within a reasonable
amount of time is the recourse to supercomputers offering several
hundreds to thousands of cores. To profit from the rapidly increasing
availability of such machines we have developed a state-of-the-art
quantum mechanical transport simulator dedicated to nanodevices and
working with four levels of parallelism. Using these four levels we
demonstrate that an almost ideal scaling of the walltime
up to 32768 processors with a parallel efficiency of 86% is reached
in the simulation of realistically extended and gated field-effect transistors.
Obtaining the current characteristics of these devices is reduced to some
hundreds of seconds instead of days on a small cluster or months on a
single CPU.
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