SC Conference - Activity Details

Liqun Cheng  (Intel Corporation)

John B. Carter  (University of Utah)

Processor and Switch Architecture

Wednesday,  11:00AM - 11:30AM

Room Ballroom F

Modern multiprocessors employ write-invalidate coherence protocols, which induce read misses to ensure consistency. Previous research has shown that an invalidate protocol is not optimal for all memory access patterns – an update protocol can significantly outperform an invalidate protocol when data is heavily shared or accessed in predictable patterns. However, update protocols can generate excessive network traffic and are difficult to build on a scalable (non-bus) interconnect. To obtain the benefits of both invalidate and update protocols, we built a speculative sequentially consistent write-update mechanism on top of a write-invalidate protocol. We present a practical and cost-effective design for extending CC-NUMA systems to support this speculative update mechanism that requires no changes to the processor core, bus interface, or memory consistency model. We also present two hardware-efficient mechanisms for detecting access patterns that benefit from the speculative update mechanism, stable reader set and stream.

The full paper can be found in the IEEE Xplore Digital Library and ACM Digital Library