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SC Conference - Activity Details



High-Performance Parallel Reconfigurable Computing: An Academic Research Platform

Author:
Guenter Knittel  (Tuebingen University)
Posters Session
Tuesday,  05:15PM - 07:00PM
Room Rotunda Lobby
Abstract:
We present our research platform for high-performance parallel reconfigurable computing. It consists of four PCs equipped with two FPGA-boards each, for a total of eight FPGA-systems. The most important feature, however, is an own-developed, dedicated interconnection network for the FPGAs. It achieves latencies below 100 nanoseconds across machines. The network consists of 16 point-to-point links, each providing a bandwidth of 2GByte/s. Accelerator functions include nearest-neighbor search in high-dimensional spaces, and distributed volume rendering. The former makes use of massively-parallel computation. For the latter, parallel accelerators work on distributed subsets of the data. This allows large datasets to be processed, but can cause frequent data exchange during rendering. This bottleneck, however, has been removed by our network. The system is beyond the proof-of-concept stage. Currently we are optimizing the design towards higher clock rates. We will give implementation details and present performance figures and comparisons to implementations on CPUs and GPUs.
   IEEE Computer Society  /  ACM     2 0   Y E A R S   -   U N L E A S H I N G   T H E   P O W E R   O F   H P C