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SC Conference - Activity Details



Adagio: Making DVS Practical for Complex HPC Applications

Authors:
Barry Rountree  (University of Georgia)
David K. Lowenthal  (University of Georgia)
Bronis R. de Supinski  (Lawrence Livermore National Laboratory)
Martin Schulz  (Lawrence Livermore National Laboratory)
Vincent W. Freeh  (North Carolina State University)
Tyler Bletch  (North Carolina State University)
Posters Session
Tuesday,  05:15PM - 07:00PM
Room Rotunda Lobby
Abstract:
Power and energy continue to be first-order design constraints in high-performance computing. Previous research using dynamic voltage scaling (DVS) has relied on trading increased execution time for energy savings. We present a novel runtime algorithm, called Adagio, that achieves significant savings with little or no delay when applied to complex, real-world load-imbalanced applications. We accomplish this by using DVS to slow selected processors during selected program regions. Adagio is based on our previous work in achieving energy savings using offline scheduling. However, as Adagio is a runtime system, we made important changes in the level of granularity, measurement of the critical path of execution, and determination of normalized execution time. We present results using Adagio for several synthetic benchmarks and two complex applications: UMT2K and ParaDiS. Adagio provides total system energy savings of 10% and 22% for these complex applications, respectively, without appreciably increasing execution time.
   IEEE Computer Society  /  ACM     2 0   Y E A R S   -   U N L E A S H I N G   T H E   P O W E R   O F   H P C