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SC Conference - Activity Details



Caching on a Chip Multi Vector Processor

Authors:
Akihiro Musa  (Tohoku University)
Yoshiei Sato  (Tohoku University)
Takashi Soga  (Tohoku University)
Ryusuke Egawa  (Tohoku University)
Hiroyuki Takizawa  (Tohoku University)
Koki Okabe  (Tohoku University)
Hiroaki Kobayashi  (Tohoku University)
Posters Session
Tuesday,  05:15PM - 07:00PM
Room Rotunda Lobby
Abstract:
Chip multiprocessors (CMPs) have become the mainstream in processor architectures. CMP architectures will be applied to vector processor design in the near future. The computational efficiency of vector supercomputers relies on their high memory bandwidth. Therefore, we propose an on-chip shared cache to maintain the effective memory bandwidth for a chip multi vector processor (CMVP). We evaluate the performance of the CMVP based on the NEC SX vector architecture using real scientific applications. Especially, the caching effects on the sustained performance are examined when the rate of the bandwidth to the performance decreases. The experimental results indicate that an 8 MB on-chip shared cache can improve the performance of a four-core CMVP by 15% to 40%, compared with that without the cache. This is because the shared cache can increase cache hit rates of multi threads.
   IEEE Computer Society  /  ACM     2 0   Y E A R S   -   U N L E A S H I N G   T H E   P O W E R   O F   H P C