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SC Conference - Activity Details



Programming the Intel 80-core Network-on-a-chip Terascale Processor

Authors:
Timothy G. Mattson  (Intel Corporation)
Rob van der Wijngaart  (Intel Corporation)
Michael Frumkin  (Google)
Papers Session
Programming Models
Wednesday,  04:30PM - 05:00PM
Room Ballroom F
Abstract:
Intel’s 80-core Terascale Processor was the first generally programmable microprocessor to break the Teraflops barrier. The primary goal for the chip was to study power management and on-die communication technologies. When announced in 2007, it received a great deal of attention for running a stencil kernel at 1.0 single precision TFLOPS while using only 97 Watts. The literature about the chip, however, focused on the hardware, saying little about the software environment or the kernels used to evaluate the chip. This paper completes the literature on the 80-core Terascale Processor by fully defining the chip’s software environment. We describe the instruction set, the programming environment, the kernels written for the chip, and our experiences programming this microprocessor. We close by discussing the lessons learned from this project and what it implies for future message passing, network-on-a-chip processors.
The full paper can be found in the IEEE Xplore Digital Library and ACM Digital Library
   IEEE Computer Society  /  ACM     2 0   Y E A R S   -   U N L E A S H I N G   T H E   P O W E R   O F   H P C