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Hiding I/O Latency with Pre-execution Prefetching for Parallel Applications

Authors:
Yong Chen  (Illinois Institute of Technology)
Surendra Byna  (Illinois Institute of Technology)
Xian-He Sun  (Illinois Institute of Technology)
Rajeev Thakur  (Argonne National Laboratory)
William Gropp  (University of Illinois at Urbana-Champaign)
Papers Session
I/O Performance
Thursday,  10:30AM - 11:00AM
Room Ballroom E
Abstract:
Parallel applications are usually able to achieve high computational performance but suffer from large latency in I/O accesses. I/O prefetching is an effective solution for masking the latency. Most of existing I/O prefetching techniques, however, are conservative and their effectiveness is limited by low accuracy and coverage. As the processor-I/O performance gap has been increasing rapidly, data-access delay has become a dominant performance bottleneck. We argue that it is time to revisit the “I/O wall” problem and trade the excessive computing power with data-access speed. We propose a novel pre-execution approach for masking I/O latency. We describe the pre-execution I/O prefetching framework, the pre-execution thread construction methodology, the underlying library support, and the prototype implementation in the ROMIO MPI-IO implementation in MPICH2. Preliminary experiments show that the pre-execution approach is promising in reducing I/O access latency and has real potential.
The full paper can be found in the IEEE Xplore Digital Library and ACM Digital Library
   IEEE Computer Society  /  ACM     2 0   Y E A R S   -   U N L E A S H I N G   T H E   P O W E R   O F   H P C