SC Conference - Activity Details

A Hybrid Data Prefetching Architecture for Data Access Efficiency

Yong Chen  (Illinois Institute of Technology)
Doctoral Research Showcase Session
Thursday,  04:45PM - 05:00PM
Room 17A/17B
While computing speed continues increasing rapidly and the multi-core/many-core processor architecture has emerged as the norm, data-access technology is lagging behind. Data-access delay, not the computation speed, becomes the identified performance bottleneck, especially for high-end/high-performance computing. We propose a Hybrid Adaptive Prefetching (HAP) architecture to bridge the gap between computing speed and data-access speed. The HAP architecture masks data-access latency effectively via two stages, processor-memory stage and memory-disk stage. It incorporates our newly proposed prefetching strategies, adaptive heuristic prediction and cooperative pre-execution prefetching together to reduce the latency of both regular and irregular accesses. We have performed extensive tests to verify the design, prototype implementation and investigate the performance improvement. The experimental testing results have confirmed significant performance gain of the HAP architecture in reducing data-access delay. The HAP architecture has a broad impact on high-end/high-performance computing to improve data-access efficiency.
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