First introduced at SC06 as the Exotic Technologies Initiative, this activity became known at SC07 as Disruptive Technologies and returns at SC08. Disruptive Technologies serves as a forum for examining those technologies that may significantly reshape the world of high performance computing in the next five to 15 years, but which are not common in todays systems. Generally speaking, a disruptive technology is a technological innovation or product that eventually overturns the existing dominant technology or product in the marketplace. Disruptive Technologies will showcase these technologies in a panel session and in a competitively selected exhibit showcase.
Disruptive Technologies Panel
Weapons of Mass Disruption
3:30-5:00PM Thursday, Nov. 20, 2008
HPC technological developments in several areas have the potential to impact exascale systems in a very disruptive way. These weapons for building exascale systems could lead to viable systems in the 2015-2020 timeframe. In this panel session, we survey four technology areas and explore their potential disruptive impacts:
- Quantum computing
- Flash storage
- Cheap and low power optical communications
- 3D chip stacking.
Moderator: Mark Seager
Dr. Seager received his B.S. degree in mathematics and astrophysics at the University of New Mexico at Albuquerque in 1979 and received his Ph.D. in Numerical Analysis from the University of Texas at Austin in 1984. Seager started working at Lawrence Livermore National Laboratory in 1983 and has been working in the field of parallel processing ever since. He manages the Platforms Program for the Advanced Simulation and Computing (ASC) Program at LLNL and has managed multiple vendor partnerships to successfully deploy architectures such as ASCI Blue Pacific (3.9 TF/s in 1998), ASCI White (12.3 TF/s in 2000) and Purple (100TF/s in 2005) and BlueGene/L (360 TF/s in 2005). In addition, Seager developed the LLNL Linux strategy and helped deploy multiple generations of leading-edge clusters. Recently Seager developed an innovative way to lower Linux Cluster TCO through the concept of building multiple clusters of various sizes from a single scalable unit design. Seager is now focused on the challenges of petascale systems, simulation environments and applications development strategies. Seager is leading the ASC Sequoia effort to deliver a 20 petaflop/s system for stockpile stewardship in 2012.
Quantum Computing: Geordie Rose
Dr. Geordie Rose is the founder and Chief Technology Officer of D-Wave Systems Inc., the world leader in the development of quantum computing systems. He is known as a leading advocate for quantum computing and physics-based processor design, and has been invited to speak on these topics in venues ranging from the 2003 TED conference to SC07. He holds a Ph.D. in theoretical physics from the University of British Columbia, specializing in quantum effects in materials. While at McMaster University, he graduated first in his class with a B.Eng. in engineering physics specializing in semiconductor engineering.
His innovative and ambitious approach to building quantum computing technology has received coverage in the Economist, the New York Times, Science magazine, MIT Technology Review, Scientific American, USA Today and HPCWire, and one of his business strategies was profiled in a Harvard Business School case study. He has received several awards and accolades for his work with D-Wave, including being short-listed for a 2005 World Technology Award, and has been granted more U.S. patents on quantum computing technology than any other inventor.
Flash Storage: Michael Cornwell
Michael Cornwell is responsible for development of solid state disk technology for server and enterprise applications at Sun Microsystems. Previously, Cornwell was the manager of storage engineering for the iPod division of Apple Inc. In this role, he was instrumental in the adoption of NAND flash in Apple products including iPod and iPhone. Prior to joining Apple, Cornwell worked at Quantum Corporation as a storage architect focused on storage management, virtual tape and disk-based backup technologies.
Cornwell holds a bachelors degree in computer science from the University of California at Santa Cruz. He has several patents pending in consumer storage and NAND flash technology and one patent awarded in enterprise storage technology.
Optical Communications: Keren Bergman
Keren Bergman is a professor of electrical engineering at Columbia University where she also directs the Lightwave Research Laboratory. Dr. Bergman received her B.S. from Bucknell University in 1988, and M.S. in 1991 and Ph.D. in 1994 from M.I.T., all in electrical engineering. At Columbia, she leads multiple research projects in optical packet switched networks, distributed grid computing over optical networks, photonic interconnection networks, nanophotonic networks-on-chip, and the applications of optical networking in high-performance computing systems. Bergman is a senior member of IEEE and a fellow of OSA. She is currently associate editor for IEEE Photonic Technology Letters and the editor-in-chief for the OSA Journal of Optical Networking.
3D stacked memory: Paul Coteus
Dr Paul Coteus has been at the IBM T.J. Watson Research Center for 20 years and is a member of IBM's Academy of Technology. He manages the Systems Packaging Group where he directs and designs advances in I/O circuits, memory system design and standardization of high speed DRAM, and high performance system packaging. He is the IBM sub-strategist for both memory and packaging research. He leads the system design and packaging of both the BlueGene/L and BlueGene/P supercomputers, and is presently working on BlueGene/Q.
Disruptive Technologies eXhibits
Changing the Semiconductor Manufacturing Paradigm
D2S enables low-volume production of SoCs and ASICs with a disruptive technology that changes the semiconductor manufacturing paradigm and is particularly suited for supercomputing applications where relatively low volumes of large chips are required. Currently, leading-edge applications make economic sense only when produced in high enough volumes to overcome the fixed costs of traditional, multi-million-dollar masks. D2S has developed new software and design technologies that make e-beam-based maskless lithography an order of magnitude faster and cheaper, while leveraging the existing hardware capabilities to make the solution a reality at 45nm and below. Maskless production of custom SoCs enables a large variety of smaller volume chips to be economically feasible. For supercomputing applications where highest density of fastest digital logic and RAM are desired, having the leading-edge nodes accessible without large volumes is important. In addition, more system testing and co-verification of software are enabled in super-computing applications by using SoC prototypes that run at speed which have been manufactured using this e-beam-based paradigm.
In DT eXhibit area, D2S will explain the VirtualMask solution and its benefits. The exhibit will demonstrate how the technology generates designs optimized for e-beam projection using the Character Projection (CP) capability.
Virtualizing the Data Center Fabric
Fulcrum Microsystems and Neterion
Data center fabric virtualization joins server and storage virtualization as a new way to cut costs and power consumption in an HPC data center. An HPC installation will often use InfiniBand for server clustering, Fibre Channel to access storage and Ethernet for LAN access; requiring NICs or HBAs for each of these connections. This presentation discusses HPC data center fabric virtualization using 10-Gigabit Ethernet to reduce those three interconnects to one. In the server, PC-Express IO Virtualization implements multiple virtual Ethernet adapters in a single NIC that are converged on a single 10-Gigabit Ethernet data flow. The fabric must support VLANs and ACLs to isolate virtual fabric domains. Class-based pause (CBP) frames and QoS are critical for lossless operation in applications such as storage. The entire solution must be optimized for the very low latency needed for both storage and HPC traffic.
In DT eXhibit area, Fulcrum Microsystems will demonstrate a Neterion IO virtualized NIC connecting to a Fulcrum switch. This demonstration will show how we can isolate traffic between two memory domains in the switch while providing guaranteed latency using congestion management and QoS features.
Auto-Analysis, Optimization and Code Generation for Parallel Computing including GPU, Multi-core CPU and other Hardware Architectures
Rogue Wave Software
At Rogue Wave Software, we are working on a technology that is designed to change the way that software development is done for parallel computing. Since CPU clock speeds stopped increasing around 2004, vendors have added processing power by increasing the number of cores in each CPU. Unfortunately, most existing software does not adequately take advantage of these additional cores. In addition, GPU (Graphics Processing Unit) hardware has moved into the realm of high-performance general purpose computing solutions. Unfortunately, writing code for these devices can be difficult and time-consuming and results in non-portable code.
Rogue Wave Project Gazelle is an auto-parallelizing source-to-source tuner and translator that simplifies the move to parallel computing by generating vendor-specific code for multi-core CPU and both GPU brands from standard C source code without having to rewrite for proprietary hardware APIs. This work is happening in cooperation with several major hardware vendors and universities.
In DT eXhibit area, Rogue Wave Software will have a live demo of the Gazelle technology to show how C code can be auto-parallelized and translated for multiple hardware devices, using all of the available CPU and GPU cores on a server for maximum throughput with minimum re-coding.
Next generation network centric FLASH memory based IOPS appliance.
Processors, driven by Moore's Law, have grown exponentially in performance, while mechanical disks, following Newtonian Dynamics, have not. Fusion-ios ioMemory technology, based on NAND Flash, creates a new tier in the memory hierarchy - one that has 100 times the capacity density and 10 times the capacity per dollar of DRAM. ioMemory makes it possible to have terabytes of near-memory-speed storage within each node - bringing extremely large memory problems and IO bound analysis to a new level of cost effectiveness. As a data staging area, ioMemory eliminates idle CPU cycles, making data loads, saves and checkpoints operate at full interconnect speed - even when faced with highly random access patterns.
In DT eXhibit area, Fusion-io will demonstrate a 4U compute node with 2 terabytes of ioMemory, achieving 4.2 gigabytes/s of bandwidth and 300,000 4K packet IOs per second.
Self Enclosed and Self-healing High Performance Lustre Storage Appliance
Terascala and their partner Xiotech have developed a disruptive scalable Lustre appliance based on self-enclosed/self healing storage. The system provides a high performance Lustre file system storage appliance in an ultra-high reliability system.
In order to maximize Lustre benefits and minimize complexity, Terascala has designed this system with unique hardware configuration options and tuned for them for both the IOPS intensive and bandwidth intensive IO processing requirements of HPC.
Taken together these two technologies produce a stunning 100x increase in storage availability and mean time between service events (MTBSE). This means you can deploy a Petabyte Lustre Appliance and expect zero service events in 5 years! By designing purpose-built systems and testing these in the harshest HPC environments such as Lawrence Livermore National Laboratory's Hyperion PetaScale testbed, Terascala provides and supports robust Lustre Appliances which dramatically simplifies the deployment, maintenance and future expansion of Lustre file systems.
In DT eXhibit area, Terascala will demonstrate their fault-tolerant and self healing Lustre system.